A20/RESET ANOMALIES

Since the 8088 only has 20 address lines, IBM decided to add extra hardware in the AT to ensure that it would emulate the 8088 memory wrap "feature." They did this by ANDING the CPU A20 with an output of the keyboard controller (KBC). Both signals must be active before the real A20 is asserted on the bus. When the KBC was programmed appropriately, it's output is always LOW. This inhibits the CPU A20 from ever being asserted on the address bus. This condition emulates the memory wrap that the 8088 has. When the keyboard controller is programmed to allow CPU A20 on the address bus, all address lines are presented without any other side effects. And when programmed to inhibit A20, nobody thought there would be any adverse side effects -- but there are.

Since CPU A20 is the only address line gated, then any memory access to extended memory on odd megabyte boundaries is inhibited (1M-2M, 3M-4M, etc.). Regardless of the state of the gate, the programmer always has access to every even megabyte of memory (0M-1M, 2M-3M, etc.). A peculiar situation arises when CPU A20 is inhibited from the address bus, and a RESET occurs. Since execution begins at the top of memory (and not F000:FFF0), when CPU A20 is gated off, the system will crash. Why? Consider CPU A20. The top of memory is FFFFF0h on the '286 and FFFFFFF0 on the '386 and later processors. If CPU A20 is gated off, then the RESET will cause execution to begin at EFFFF0 on the '286 and FFEFFFF0 on the '386. Unless these addresses are mapped through hardware to appear at the top of memory, then the computer will crash -- as it will try and execute whatever lies at these addresses (most likely a floating BUS).

The moral to the story? Don't ever RESET the CPU without enabling CPU A20 to the address BUS.

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